Region Control Oriented Stacked CMOS Image Sensor with Array-Parallel ADC Architecture

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  • 領域制御を指向したアレイ並列アーキテクチャに基づく積層型CMOSイメージセンサ

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Description

A 4.1Mpix 280fps stacked CMOS image sensor with array-parallel ADC architecture is developed for region control applications. The combination of an active reset scheme and frame correlated double sampling (CDS) operation cancels Vth variation of pixel amplifier transistors and kTC noise. The sensor utilizes a floating diffusion (FD) based back-illuminated (BI) global shutter (GS) pixel with 2.4e-rms readout noise. An intelligent sensor system with face detection and high resolution region-of-interest (ROI) output is demonstrated with significantly low data bandwidth and low ADC power dissipation by utilizing a flexible area access function.

Journal

  • ITE Technical Report

    ITE Technical Report 41.32 (0), 35-38, 2017

    The Institute of Image Information and Television Engineers

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