Present Status of Thin Film Technology Applied for Si ULSI and Expectation of Their Problem Solution Created by the University Researchers

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  • Si ULSI用薄膜技術の現状と課題
  • Si ULSIヨウ ハクマク ギジュツ ノ ゲンジョウ ト カダイ

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Abstract

Silicon ULSI-Ultra Large Scale Integration-is the key component for the information age in 1990's. Among the ULSI's, memory devices are the driving vehicles of high end technology. Bit density of the memory devices has been generally increased 4 times every 3 years. The most important processes used for the advanced memory fabrication are as follows; i) memory cell technology: a planar capacity of a memory cell has been used for smaller scale memory than 1 mega-bit, while 3 dimensional memory cell such as a stacked capacitor cell and a trench cell has been utilized for the memory larger than 4 mega-bit, to increase the capacitance of the smaller cell. Moreover, the films with larger dielectric constant such as Ta_2O_5, SrTiO_3 and PZT (Pb(Zr, Ti)O_3) have been intensively investigated. ii) multi-level metallization technology of fine patterning: planarization and stress reduction have been strongly required for the 3 dimensional memory cell and the multi-level metallization. Integrated planarization, therefore, has been investigated for the substrate, metallization and insulating film between multi-level interconnection. For the planarized insulating film, TEOS-O_3 SiO_2 Film has been strongly developed. Problems of the thin film technology higher than 64 mega-bit memory are summarized in the total field of new technology including new material, new equipment, simulation, and evaluation. Breakthroughs for these problems are expected, created on the basis of fresh concept by the university researchers.

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