On Improvements of a SAT-Solver PCMGTP on FPGA

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  • Fujita Hiroshi
    Department of Intelligent Systems, Faculty of Information Science and Electrical Engineering, Kyushu University
  • Hasegawa Ryuzo
    Department of Intelligent Systems, Faculty of Information Science and Electrical Engineering, Kyushu University
  • Koshimura Miyuki
    Department of Intelligent Systems, Faculty of Information Science and Electrical Engineering, Kyushu University
  • Kinoshita Shohei
    Department of Intelligent Systems, Graduate School of Information Science and Electrical Engineering, Kyushu University : Master's Program
  • Matsuda Jun'ichi
    Department of Intelligent Systems, Graduate School of Information Science and Electrical Engineering, Kyushu University : Master's Program

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  • PGA上のSATソルバPCMGTPの改良について
  • FPGA上のSATソルバPCMGTPの改良について
  • FPGA ジョウ ノ SAT ソルバ PCMGTP ノ カイリョウ ニ ツイテ

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Abstract

In this paper, an improved design of a SAT-solver PCMGTP on FPGA is described. The previous implementation of PCMGTP achieved considerable speedup of SAT-solving compared to the software counterpart of MGTP. After intensive analyses and experiments, it turned out that the early design contains much redundancy and has room for improvement. Also, we developed a generic description style in Verilog using arrays and iterative constructs. Experimental results show that the new implementation outperforms the old one with regard to both execution time and circuit size.

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