画素選択型テンプレートマッチングのFPGA化における回路規模削減手法の提案

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  • Circuit Size Reduction Method for FPGA Implementation of Template Matching Using Limited Pixels

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<p>This paper introduces a circuit size reduction method in FPGA implementation for template matching using limited pixels. Template matching is a simple method but requires a large amount of processing time. So, it's necessary to speed up the template matching method for practical use requiring real-time processing. To speed up the processing, it's effective to use an FPGA circuit instead of a CPU as well as limitation of pixels used in matching process. In the circuit design, parallelization contributes to reduction of processing time, but circuit size increases. The proposed method can reduce the circuit size by setting certain restrictions on pixel selection. Through experiments using 4type×121 images, we confirmed that the proposed method can reduce the circuit size by 20% while suppressing the deterioration of matching accuracy. This circuit of matching algorithm can process 512×512 pixels input image and 128×128 pixels template image in 0.7 milliseconds.</p>

収録刊行物

  • 精密工学会誌

    精密工学会誌 90 (1), 138-144, 2024-01-05

    公益社団法人 精密工学会

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