An integrated capacitor-less LDO with transient and stability enhancement

DOI Web Site 参考文献30件
  • Xie Yafei
    Institute of Microelectronics of the Chinese Academy of Sciences University of Chinese Academy of Sciences Key Laboratory of Science and Technology on Silicon Devices, Chinese Academy of Sciences
  • Cai Xiaowu
    Institute of Microelectronics of the Chinese Academy of Sciences Key Laboratory of Science and Technology on Silicon Devices, Chinese Academy of Sciences
  • Lu Yu
    Institute of Microelectronics of the Chinese Academy of Sciences University of Chinese Academy of Sciences Key Laboratory of Science and Technology on Silicon Devices, Chinese Academy of Sciences
  • Dang Jianying
    Institute of Microelectronics of the Chinese Academy of Sciences University of Chinese Academy of Sciences Key Laboratory of Science and Technology on Silicon Devices, Chinese Academy of Sciences
  • Pan Longli
    Institute of Microelectronics of the Chinese Academy of Sciences Key Laboratory of Science and Technology on Silicon Devices, Chinese Academy of Sciences
  • Gao Mali
    Institute of Microelectronics of the Chinese Academy of Sciences
  • Wang Lei
    Institute of Microelectronics of the Chinese Academy of Sciences Key Laboratory of Science and Technology on Silicon Devices, Chinese Academy of Sciences
  • Li Bo
    Institute of Microelectronics of the Chinese Academy of Sciences Key Laboratory of Science and Technology on Silicon Devices, Chinese Academy of Sciences

抄録

<p>A novel capacitor-less low-dropout regulator (CL-LDO) is presented that achieves transient and stability enhancements through the addition of an active capacitor and a dynamically biased buffer. To enhance the transient response, an active capacitor is proposed, resulting in a significant reduction in overshoot, undershoot, and settling time. Furthermore, the dynamically-biased buffer, comprised of a super-gm source follower, effectively enhances the loop stability. Implemented and fabricated in 0.18µm SOI BCD technology, the CL-LDO generates a stable output voltage of 1.8V in the input voltage range from 2.8V to 3.8V, with a maximum load current of 100mA and a quiescent current of 94µA. When the load current steps from 0mA to 100mA, the measured results of overshoot and undershoot are 240mV and 110mV, respectively. The proposed CL-LDO has superior line regulation of 0.94mV/V and load regulation of 12.66mV/A.</p>

収録刊行物

  • IEICE Electronics Express

    IEICE Electronics Express 21 (9), 20240199-20240199, 2024-05-10

    一般社団法人 電子情報通信学会

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