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Design of a Low-Area 4-bit Carry Lookahead Adder Using Clockless Logic Gates with Superconducting Single Flux Quantum Circuits
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- Fujisawa Taisei
- Yokohama National Univ.
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- Yamanashi Yuki
- Yokohama National Univ.
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- Yoshikawa Nobuyuki
- Yokohama National Univ.
Bibliographic Information
- Other Title
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- 超伝導単一磁束量子回路によるクロックレス論理ゲートを用いた低面積4bit桁上げ先取り加算器の設計
Journal
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- JSAP Annual Meetings Extended Abstracts
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JSAP Annual Meetings Extended Abstracts 2022.1 (0), 1851-1851, 2022-02-25
The Japan Society of Applied Physics
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Details 詳細情報について
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- CRID
- 1390866882741635840
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- ISSN
- 24367613
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- Text Lang
- ja
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- Data Source
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- JaLC
