Methodology for Evaluating Operation Temperatures of Fin-Type Field-Effect Transistors Connected by Interconnect Wires

Tsunaki Takahashi, Shunri Oda, Ken Uchida

doi:10.7567/jjap.52.064203

<jats:p> A new methodology for evaluating operation temperatures of transistors connected by interconnect wires is developed. Thermal characteristics of fin-type field-effect transistors (FinFETs) and interconnect wires are modeled using simple equivalent thermal circuits. The temperature nodes are the source, drain, gate, substrate, and hot spot, where the lattice temperature is the highest. By calculating heat flows from the hot spot to the other four nodes, the thermal resistances <jats:italic>R</jats:italic> <jats:sub>th</jats:sub>'s for bulk and silicon-on-insulator (SOI) FinFETs are extracted. It is shown that the source <jats:italic>R</jats:italic> <jats:sub>th</jats:sub> is higher than the drain <jats:italic>R</jats:italic> <jats:sub>th</jats:sub> because of asymmetric temperature distributions in the device. The thermal resistances of interconnect wires and vias are given as analytical expressions. By combining the device <jats:italic>R</jats:italic> <jats:sub>th</jats:sub>'s and the analytical <jats:italic>R</jats:italic> <jats:sub>th</jats:sub>'s for the interconnect wires and vias, device temperatures can be obtained. The validity of the proposed methodology was confirmed by temperature simulations of a circuit where two devices were connected in parallel. It is demonstrated that high-thermal-conductivity interconnect materials, such as carbon nanotubes, are effective for lowering device temperatures when interconnects are extremely downscaled such as systems at the 14 nm technology node. </jats:p>

Methodology for Evaluating Operation Temperatures of Fin-Type Field-Effect Transistors Connected by Interconnect Wires

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