Double junction tunnel using Si nanocrystalline layer for nonvolatile memory devices
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<jats:p> A novel nonvolatile memory tunnel layer structure is proposed in which a Si nanocrystalline layer lies between double tunnel oxides. By Si nanocrystal size downscaling to 2 nm, the new double junction tunnel attains a remarkable 3×10<jats:sup>6</jats:sup> times retention improvement while keeping high-speed write/erase compared to single tunnel oxide. Based on Si nanocrystal size confirmation by transmission electron microscope (TEM), we show quantitatively that the advantage is due to Coulomb blockade and quantum confinement, and smaller Si nanocrystal will lead to greater improvement. We clarify a characteristic effect in double junction tunnel, tunnel penetration disappearance, which is extremely advantageous for nonvolatile memory applications and never occurs in other multilayer dielectrics structures. The double tunnel junction using Si nanocrystalline layer is very promising for future memory. </jats:p>
収録刊行物
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- Japanese journal of applied physics : JJAP
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Japanese journal of applied physics : JJAP 50 (4), 041302-, 2011-04
Tokyo : The Japan Society of Applied Physics
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詳細情報 詳細情報について
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- CRID
- 1520290882625859968
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- NII論文ID
- 40018800869
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- NII書誌ID
- AA12295836
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- ISSN
- 00214922
- 13474065
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- NDL書誌ID
- 11075383
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- 本文言語コード
- en
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- NDL 雑誌分類
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- ZM35(科学技術--物理学)
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- データソース種別
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- NDL
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