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FPGAを用いた可変連想度セットアソシエイティブキャッシュによる充足/最大充足可能性問題の高速計算

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Other Title
  • FPGA オ モチイタ カヘン レンソウド セットアソシエイティブキャッシュ ニ ヨル ジュウソク/サイダイ ジュウソク カノウセイ モンダイ ノ コウソク ケイサン
  • FPGAを用いた可変連想度セットアソシエイティブキャッシュによる充足/最大充足可能性問題の高速計算 (リコンフィギャラブルシステム)
  • FPGA Acceleration of SAT/MaxSAT Solving using Variable-way Set Associative Cache
  • リコンフィギャラブルシステム
  • リコンフィギャラブル システム

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Abstract

WalkSAT (WSAT) is one of the stochastic local search algorithms for Boolean Satisfiability (SAT) and Maximum Boolean Satisfiability (MaxSAT), and it is very suitable for hardware acceleration, because of its high inherent parallelism. Formal verification is one of the most important applications of SAT and MaxSAT, however, the size of the formal verification problems is significantly larger than on-chip memory size, and most of the data have to be placed in off-chip DRAM. In this approach, however, the acceleration was still limited by the DRAM access delay. In this paper, we propose a method to hide the access delay by using on-chip memory banks as a variable-way associative cache memory. With this cache memory, up to 60% DRAM access delay can be hidden, and the performance can be improved up to 26%.

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Keywords

Details

  • CRID
    1520290884437699200
  • NII Article ID
    110009925735
  • NII Book ID
    AA1123312X
  • ISSN
    09135685
  • NDL BIB ID
    025590086
  • Web Site
    http://id.ndl.go.jp/bib/025590086
  • Text Lang
    ja
  • NDL Source Classification
    • ZN33(科学技術--電気工学・電気機械工業--電子工学・電気通信)
  • Data Source
    • NDL
    • CiNii Articles

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