- 【Updated on May 12, 2025】 Integration of CiNii Dissertations and CiNii Books into CiNii Research
- Trial version of CiNii Research Knowledge Graph Search feature is available on CiNii Labs
- Suspension and deletion of data provided by Nikkei BP
- Regarding the recording of “Research Data” and “Evidence Data”
A transistor-level symmetrical layout generation method for analog device
Bibliographic Information
- Other Title
-
- A transistor level symmetrical layout generation method for analog device
- VLSI設計技術
- VLSI セッケイ ギジュツ
Search this article
Journal
-
- 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報
-
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 111 (216), 1-4, 2011-09
東京 : 電子情報通信学会
- Tweet
Details 詳細情報について
-
- CRID
- 1520853834068897408
-
- NII Article ID
- 110008900274
-
- NII Book ID
- AN10013323
-
- ISSN
- 09135685
-
- NDL BIB ID
- 11270977
-
- Text Lang
- en
-
- NDL Source Classification
-
- ZN33(科学技術--電気工学・電気機械工業--電子工学・電気通信)
-
- Data Source
-
- NDL Search
- CiNii Articles