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Memory Fault Analysis using an EB Tester
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- Hamada Hiroyuki
- A&E Technology Center,NEC Corp.
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- Tsujide Tohru
- A&E Technology Center,NEC Corp.
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- Nakaizumi Kazuo
- A&E Technology Center,NEC Corp.
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- Hishii Toshiyasu
- A&E Technology Center,NEC Corp.
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- Saito Shinichi
- Second electronics Division,Naito Densei Corp.
Bibliographic Information
- Other Title
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- EBテスタによるメモリの故障解析
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Description
Because of increasing die size and higher circuit integration in LSI technology,failure analysis of LSIs is becoming more difficult and time-cosuming.LSI fault localization method,using voltage contrast image developed by NEC,is very effective in reducing failure analysis time.The method has been applied to failure analysis of many kinds of Logic LSI,and we have succeeded in analyzing the samples in 90%of cases.
Journal
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- IEICE technical report. Reliability
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IEICE technical report. Reliability 93 (522), 53-58, 1994-03-18
The Institute of Electronics, Information and Communication Engineers
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Details 詳細情報について
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- CRID
- 1570009752536821504
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- NII Article ID
- 110003302215
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- NII Book ID
- AN10013243
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- Text Lang
- ja
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- Data Source
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- CiNii Articles
