High Speed Layout Synthesis for Minimum-Width CMOS Logic Cells via Boolean Satisfiability
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- IIZUKA Tetsuya
- Department of Electronic Engineering, and VLSI Design and Education Center (VDEC), The University of Tokyo
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- IKEDA Makoto
- Department of Electronic Engineering, and VLSI Design and Education Center (VDEC), The University of Tokyo
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- ASADA Kunihiro
- Department of Electronic Engineering, and VLSI Design and Education Center (VDEC), The University of Tokyo
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説明
This paper proposes a cell layout synthesis method via Boolean Satisfiability (SAT). Cell layout synthesis problems are first transformed into SAT problems by our formulations. Our method realizes a high-speed layout synthesis for CMOS logic cells and guarantees to generate the minimum-width cells with routability under our layout styles. It considers complementary P-/N-MOSFETs individually during transistor placement, and can generate smaller width layout compared with pairingthe complementary P-/N-MOSFETs case. To demonstrate the effectiveness of our SAT-based cell synthesis, we present experimental results which compare it with the 0-1 ILP-based transistor placement method and a commercial cell generation tool. The experimental results show that our SAT-based method can generate minimum-width placements in much shorter run time than the 0-1 ILP-based transistor placement method, and can generate the cell layouts of 32 static dual CMOS logic circuits in 54% run time compared with the commercial tool. Area increase of our method without compaction is only 3% compared with the commercial tool with compaction.
収録刊行物
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- IEICE transactions on fundamentals of electronics, communications and computer sciences
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IEICE transactions on fundamentals of electronics, communications and computer sciences 87 (12), 3293-3300, 2004-12-01
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詳細情報 詳細情報について
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- CRID
- 1570009752557569664
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- NII論文ID
- 110003212869
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- NII書誌ID
- AA10826239
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- ISSN
- 09168508
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- 本文言語コード
- en
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- データソース種別
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- CiNii Articles