Error detection using residue signed-digit number arithmetic for arithmetic circuits

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Other Title
  • 剰余SD数演算回路を用いた算術演算誤り検出

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Description

For error detection of multiply-accumulate operation, a residue error detector can be considered for the VLSI implementation with compact and high speed performance. In this paper, we propose an error detection circuit using a binary tree of an efficient residue Signed-Digit (SD) number adders, in which the residue SD addition is performed in the same constant time as an SD adder. In detail, the circuits for converting the binary numbers to residue SD numbers and residue SD multiplication are designed in the structure of binary SD adder trees. We merge the trees into efficient adder tree with the least addition stages. We also discuss the relationship between the error bits and the moduli. All two-bit errors of arithmetic can be detected by selecting two moduli. The design experiments show that the proposed error detection circuits are high speed comparing to that using the binary arithmetic.

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Details 詳細情報について

  • CRID
    1570009752931287936
  • NII Article ID
    110009868159
  • NII Book ID
    AA11451459
  • ISSN
    09196072
  • Text Lang
    ja
  • Data Source
    • CiNii Articles

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