Average Power Reduction in Scan Testing by Test Vector Modification

2 Citations 12 References
  • KAJIHARA Seiji
    Graduate School of Computer Science and Systems Engineering, Kyushu Institute of technology
  • ISHIDA Koji
    Graduate School of Computer Science and Systems Engineering, Kyushu Institute of technology
  • MIYASE Kohei
    Graduate School of Computer Science and Systems Engineering, Kyushu Institute of technology

Search this article

Description

This paper presents a test vector modification method for reducing average power dissipation during test application for a full-scan circuit. The method first identifies a set of don't care (X) inputs of given test vectors, to which either logic value 0 or 1 can be assigned without losing fault coverage. Then, the method reassigns logic values to the X inputs so as to decrease switching activity of the circuit during scan shifting. Experimental results for benchmark circuits show the proposed method could decrease switching activity of a given test set to 45% of the original test sets in average.

Journal

  • IEICE Trans. Info. and Syst., D

    IEICE Trans. Info. and Syst., D 85 (10), 1483-1489, 2002-10-01

    The Institute of Electronics, Information and Communication Engineers

Citations (2)*help

See more

References(12)*help

See more

Keywords

Details 詳細情報について

  • CRID
    1570291227307159296
  • NII Article ID
    110006376577
  • NII Book ID
    AA10826272
  • ISSN
    09168532
  • Text Lang
    en
  • Data Source
    • CiNii Articles

Report a problem

Back to top