Test pattern generation for the circuits generated by using General Shannor Expansion

Bibliographic Information

Other Title
  • 一般シャノン展開を用いて合成される論理回路に対するテストパターンの生成

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Description

General Shannon Expansion(GSE)is a logic expansion on an n-tuple of expressions(v1,v2,...,vn)where v_iv_j=0(i j)and Σi=,..,n vi=1.T he tuple is know as orthonormal system.Separation of the variables among the system and coefficients still alows us to design 100% stuck-at fault testable 4 level logic circuit for any given logic function.The tests for stuck-at 0 faults are generated by choosing each element of the system one by one.The tests for stuck-at 1 faults are generarated by investigating the overlapping of the ″ne ighboring terms″ that are created by negating a literal of origina l prime implicants in GSE.

Journal

  • Technical report of IEICE. FTS

    Technical report of IEICE. FTS 93 (459), 1-6, 1994-02-10

    The Institute of Electronics, Information and Communication Engineers

Keywords

Details 詳細情報について

  • CRID
    1570291227426253568
  • NII Article ID
    110003206898
  • NII Book ID
    AN10012998
  • Text Lang
    ja
  • Data Source
    • CiNii Articles

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