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A Novel Power-Off Mode for A Battery-Backup DRAM
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- TAKASHIMA D.
- ULSI Research Laboratories, Research and Development Center, TOSHIBA Corporation
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- OOWAKI Y.
- ULSI Research Laboratories, Research and Development Center, TOSHIBA Corporation
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- WATANABE S.
- ULSI Research Laboratories, Research and Development Center, TOSHIBA Corporation
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- OHUCHI K.
- ULSI Research Laboratories, Research and Development Center, TOSHIBA Corporation
Bibliographic Information
- Other Title
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- 超低スタンドバイ電流DRAMの検討
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Description
This paper proposes a new DRAM power-off mode, in which power source is completely shut off during stand-by, resulting zero stand-by leakage current. By introducing a new word-line's power-on/off sequence and a ground plate design, the cell data in a 64KbDRAM test device was maintained even after power source was turned on/off. The measured power-off time was as long as the measured data retention time of the conventional DRAM.
Journal
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- IEICE technical report. Electron devices
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IEICE technical report. Electron devices 95 (117), 9-14, 1995-06-23
The Institute of Electronics, Information and Communication Engineers
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Keywords
Details 詳細情報について
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- CRID
- 1570291227426468608
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- NII Article ID
- 110003200235
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- NII Book ID
- AN10012954
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- Text Lang
- ja
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- Data Source
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- CiNii Articles
