Single-Chip 4-Channel 155Mb/s CMOS LSI Chip for ATM Physical Layer Controller(QPLC)

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Bibliographic Information

Other Title
  • 155Mb/s対応4ポート入り1チップATM物理層制御用LSI(QPLC)

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Description

To introduce ATM (Asynchronous Transfer Mode) to mass application, it is desirable to reduce the ATM switch board area, while maintaining high data speed and low jitter. A 4 ports CMOS single chip LSI, QPLC (Quad Physical Layer Controller), has been developed to fulfill the requirement by integrating 4 receive/transmit ports, each of which has a clock recovery PLL (Phase Locked Loop). QPLC supports three bit rates, i.e., 155.52, 51.84 and 25.92 Mb/s and it restricts interference between ports, which makes jitter large, by the triple well structure and the differential ring oscillator type VCO (Voltage Controlled Oscillator).

Journal

  • Technical report of IEICE. ICD

    Technical report of IEICE. ICD 97 (229), 25-32, 1997-08-21

    The Institute of Electronics, Information and Communication Engineers

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Details 詳細情報について

  • CRID
    1570291227507587840
  • NII Article ID
    110003316618
  • NII Book ID
    AN10013276
  • Text Lang
    ja
  • Data Source
    • CiNii Articles

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