Logic Optimization: Redundancy Addition and Removal Using Implication Relations
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- ICHIHARA Hideyuki
- Department of Applied Physics, Faculty of Engineering, Osaka University
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- KINOSHITA Kozo
- Department of Applied Physics, Faculty of Engineering, Osaka University
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抄録
The logic optimization based on redundancy addition and removal is one of methods which can deal with largescale logic circuits. In this logic optimization a few redundant elements are added to a logic circuit, and then many other redundant elements which are generated by the redundancy addition are identified and removed. In this paper an optimization method based on redundancy addition and removal using implication relations is proposed. The advantage of the proposed method is to identify removable redundant elements with short time, because the proposed method directly identifies redundant elements using implication relations from two illegal signal assignments which are produced by redundancy addition. The experimental results compared this method with another method show that this method is faster than the another method without declining the optimization ability.
収録刊行物
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- IEICE transactions on information and systems
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IEICE transactions on information and systems 81 (7), 724-730, 1998-07-25
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詳細情報 詳細情報について
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- CRID
- 1570291227535606400
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- NII論文ID
- 110003219786
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- NII書誌ID
- AA10826272
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- ISSN
- 09168532
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- 本文言語コード
- en
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- データソース種別
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- CiNii Articles