Enhancing Instruction Fetch Width by Grouping Multiple Basic Blocks

SATO Toshinori

Bibliographic Information

Other Title

基本ブロックの動的再配置による命令フェッチ幅の向上

Description

In this paper, the performance evaluation of several processor models attached with the non-consective basic block buffer (NCB) is presented. The NCB is an extension of the branch target buffer, and enlarges the effective instruction fetch bandwidth, Thus, the instruction fetching efficiency is improved and the instruction level palallelism is exploited. From the experimental evaluation, it is found that the NCB is effective for the wide range of multiple issue processors.

Journal

IPSJ SIG Notes

IPSJ SIG Notes 125 103-108, 1997-08-20

Information Processing Society of Japan (IPSJ)

Details 詳細情報について

CRID: 1570572702109938176

NII Article ID: 110002774716

NII Book ID: AN10096105

ISSN: 09196072

Text Lang: ja

Data Source

CiNii Articles

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