Low Power Consumption Arithmetic Units in the"Plastic Hard Macro Technology"

Bibliographic Information

Other Title
  • プラスチック・ハード・マクロ技術による低消費電力算術演算器

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Description

A design methodology/porting methodology for high-speed and low power arithmetic units library is proposed, which is called the "Plastic Hard Macro Technology". The key design feature is co-operating design optimization among circuit(netlist)design, cell design, and layout design. A primary target is significant reduction of the energy-delay product. A dedicated symbolic layout tool helps the cell design and porting to different processes. A 16-bit multiplier is designed for an example and ported to five different processes. Approximately 50% ED product reduction is attained, which is conpared with conventional multiplier design. Very small porting cost is also realized.

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Details 詳細情報について

  • CRID
    1570572702149434880
  • NII Article ID
    110002676012
  • NII Book ID
    AA11451459
  • ISSN
    09196072
  • Text Lang
    ja
  • Data Source
    • CiNii Articles

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