A study on arithmetic accelerators for on-chip memory processor

Bibliographic Information

Other Title
  • オンチップメモリプロセッサでの演算加速機構の検討(プロセッサ・アーキテクチャ(2),「ハイパフォーマンスコンピューティングとアーキテクチャの評価」に関する北海道ワークショップ(HOKKE-2007))

Search this article

Description

In this paper, we study a design of arithmetic accelerators to integrate the accelerator into on-chip memory processor, which is expected to be effective to improve power performance. We propose vector-type arithmetic accelerators and SIMD-type arithmetic accelerators. The results of preliminary evaluation using simple vector loops, which is suited to vector-type accelerators, indicates that address calculation by scalar processor is a bottleneck in SIMD-type accelerators. We present how to improve the performance of SIMD-type accelerator for such problems. We have also examined many aspects including the power performance for both accelerators, which still needs further investigation by simulation.

Journal

  • IPSJ SIG Notes

    IPSJ SIG Notes 2007 (17), 263-268, 2007-03-01

    Information Processing Society of Japan (IPSJ)

Details 詳細情報について

  • CRID
    1570572702292930688
  • NII Article ID
    110006248453
  • NII Book ID
    AN10463942
  • Text Lang
    ja
  • Data Source
    • CiNii Articles

Report a problem

Back to top