A Data Path Scheduling Algorithm with Resource Allocation for DSP Synthesis

2 Citations 16 References
  • NISHIDA Koichi
    Dept. of Electronics and Communication Engineering Waseda University
  • TOGAWA Nozomu
    Dept. of Electronics and Communication Engineering Waseda University
  • SATO Masao
    Dept. of Electronics and Communication Engineering Waseda University
  • OHTSUKI Tatsuo
    Dept. of Electronics and Communication Engineering Waseda University

Bibliographic Information

Other Title
  • リソースアロケーションを考慮したデータパス・スケジューリング手法

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Description

In high-level synthesis for DSP data paths, scheduling of data flow graphs plays a primary role. In scheduling, it is required that a hardware resource amount is estimated as precisely as possible, and that operations are assigned to control steps so that a resource amount is minimized. In addition, pipelining that overlaps operations is necessary in high-speed DSP application such as image processing. In this paper, we propose a time constraint scheduling algorithm that deals with pipelining, and minimizes both functional unit and register costs. In our algorithm, the control step regarded as the worst in terms of a resource cost is gradually eliminated for each operation in each iteration. Finally, each operation is assigned to one control step. Experimental results for practical DSP data flow graphs show that our algorithm obtains near optimal solutions in less than one second.

Journal

  • Technical report of IEICE. VLD

    Technical report of IEICE. VLD 95 (307), 63-70, 1995-10-20

    The Institute of Electronics, Information and Communication Engineers

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Keywords

Details 詳細情報について

  • CRID
    1570572702386479104
  • NII Article ID
    110003294740
  • NII Book ID
    AN10013323
  • Text Lang
    ja
  • Data Source
    • CiNii Articles

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