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TCAD/DA for ASIC and MPU Development
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- MASUDA Hiroo
- Hitachi, Ltd.
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- SATO Hisako
- Hitachi, Ltd.
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- TSUNENO Katsumi
- Hitachi, Ltd.
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- MORI Kazutaka
- Hitachi, Ltd.
Bibliographic Information
- Other Title
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- ASICおよびMPU開発のTCAD/DA
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Description
We have proposed, in this paper a, TCAD/DA methodology for MPU and ASIC with updated processes and devises, which allow a predictive chip-design with quick quantitative correlation studies between process-recipe and CKT & delay parameters required in DA works. Effects of statistical process variation on 0.35um CMOS have been rigorously characterized with a new global TCAD calibratoin technique.Based on the deta, process variation effects on a 0.25um CMOS have been predicted, which is concluded that the Vth and Ids total-variation of the 0.25um CMOS shows less than 10% in production process, which is similar with that of the 0.35um CMOS.
Journal
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- Technical report of IEICE. ICD
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Technical report of IEICE. ICD 97 (579), 55-61, 1998-03-06
The Institute of Electronics, Information and Communication Engineers
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Details 詳細情報について
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- CRID
- 1570572702483695488
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- NII Article ID
- 110003316756
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- NII Book ID
- AN10013276
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- Text Lang
- ja
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- Data Source
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- CiNii Articles