A RTL Partitioning Method with a Fast Min-Cut Improvement Algorithm

6 References
  • KAWAGUCHI Kenichi
    Corporate Semiconductor Development Division, Matsushita Electric Industrial Co., Ltd.
  • KABUO Chie
    Corporate Semiconductor Development Division, Matsushita Electric Industrial Co., Ltd.
  • MURAOKA Michiaki
    Corporate Semiconductor Development Division, Matsushita Electric Industrial Co., Ltd.

Bibliographic Information

Other Title
  • 高速 Min-Cut アルゴリズムを用いたRTレベル回路分割手法

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Description

A design flow with register-transfer-level(RT-level)partitioning and a RT-level partitioning algorithm forefficient logic synthesis and layout are described in this paper.Changing the parameter of partitioning optimization dynamically, the algorithm improves an interconnection cost in a short CPU time.Experimental results on large circuits show that the algorithm partitioned circuits with the large number of RT-level components in a tenth to a hundredth of conventional partitioning times.

Journal

  • Technical report of IEICE. VLD

    Technical report of IEICE. VLD 97 (577), 87-94, 1998-03-06

    The Institute of Electronics, Information and Communication Engineers

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Keywords

Details 詳細情報について

  • CRID
    1570854177362476544
  • NII Article ID
    110003294566
  • NII Book ID
    AN10013323
  • Text Lang
    ja
  • Data Source
    • CiNii Articles

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