A Logic Optimization Method for lange Scale Circuits by Logic Partitioning

Nakamura Yuichi

Bibliographic Information

Other Title

論理分割を使った大規模回路最適化の一手法

Description

This paper presents the logic partition method to optimize the large scale circuits.The proposed logic partition method find out the sub-circuits which are able to optimized.However,there is the property that given two sub-circuits cannot be optimized between them,if they have no common transitive fanin.The proposed method can find common transitive fanin very quickly,because the method constructs the matrix to presents the transitive fanin information. And then,the method extract the rectangle from the matrix.Also, after the proposed method,the logic optimization methods are applied to the partitioned circuits in experimental results.

Journal

Technical report of IEICE. FTS

Technical report of IEICE. FTS 94 49-54, 1994

The Institute of Electronics, Information and Communication Engineers

Keywords

Details 詳細情報について

CRID: 1570854177377528192

NII Article ID: 110003194261

NII Book ID: AN10012998

Text Lang: ja

Data Source

CiNii Articles

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