A 286MHz 64-bit Floating Point Multiplier with Enhanced CG Operation

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Bibliographic Information

Other Title
  • CGに適した機能を有する286MHz、64ビット浮動小数点乗算器

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Description

This paper presents a high speed 64-bit floating-point (FP) multiplier with a useful function for computer graphics (CG). The critical path delay was minimized by selecting high speed gates and limiting the stage number of series transmission gates (TGs). We implemented the special function of "CG multiplication" that directly multiplies a pixel data by a FP data. The process technology is 0.5-μm CMOS with triple metal. The active area size is 4.2×5.1mm^2. The operating frequency is 286MHz at the supply voltage of 3.3V. Implementation of CG multiplication increases the transistor count only 4%. Also, it has no effect on the delay in the critical path.

Journal

  • Technical report of IEICE. DSP

    Technical report of IEICE. DSP 95 (298), 13-20, 1995-10-19

    The Institute of Electronics, Information and Communication Engineers

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Keywords

Details 詳細情報について

  • CRID
    1570854177462146688
  • NII Article ID
    110003279819
  • NII Book ID
    AN10060786
  • ISSN
    09135685
  • Text Lang
    ja
  • Data Source
    • CiNii Articles

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