A Compact Radix-64 54 × 54 CMOS Redundant Binary Parallel Multiplier

参考文献16件
  • LEE Sang-Hoon
    High-Speed CMOS IC Lab. Department of Electrical Engineering, Pohang University of Science and Technology (POSTECH)
  • BAE Seung-Jun
    High-Speed CMOS IC Lab. Department of Electrical Engineering, Pohang University of Science and Technology (POSTECH)
  • PARK Hong-June
    High-Speed CMOS IC Lab. Department of Electrical Engineering, Pohang University of Science and Technology (POSTECH)

この論文をさがす

説明

The radix-64 encoding scheme was used to reduce the number of partial products in the 54 × 54 CMOS parallel multiplier. The transistor counts, the chip area and the power-delay product were reduced by 28% 22%, and 17%, respectively, compared to any of the published 54 × 54 CMOS parallel multipliers. A redundant binary (RB) number system was used to represent any of the 65 multiplying coefficients as a RB numher which consists of two of 9 fundamental multiplying coefficients and their complements. The resultant RB partial products were added by using optimized RB adders. The total transistor count of the proposed multiplier was 43,579. The chip area in 0.25 μm CMOS process with 5 metal layers was 0.99 mm^2. The power consumption and the multiplication time were 111mW and 6.9ns, respectively.

収録刊行物

参考文献 (16)*注記

もっと見る

キーワード

詳細情報 詳細情報について

  • CRID
    1570854177489077376
  • NII論文ID
    110003212395
  • NII書誌ID
    AA10826283
  • ISSN
    09168524
  • 本文言語コード
    en
  • データソース種別
    • CiNii Articles

問題の指摘

ページトップへ