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Optimization of Sequential Circuits using Retiming and Redundancy Removal
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- YOTSUYANAGI Hiroyuki
- Department of Applied Physics, Faculty of Engineering, Osaka University
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- KAJIHARA Seiji
- Department of Applied Physics, Faculty of Engineering, Osaka University
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- KINOSHITA Kozo
- Department of Applied Physics, Faculty of Engineering, Osaka University
Bibliographic Information
- Other Title
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- リタイミングと冗長除去を用いた順序回路の簡単化
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Description
The existence of sequential redundancy in logic circuits will have bad effects on chip size and testability of sequential circuits. In this paper we propose a redundancy removal method for reducing the number of gates and flip-flops. The proposed method is comprised of redundancy removal using a combinational test generator and retiming. Retiming is utilized for two purposes: One is for finding sequential redundancies and another is for reducing the number of flip-flops. Applying redundancy removal techniques after retiming, not only all combinational redundancies but also several sequential redundancies can be removed. Experimental results for ISCAS'89 benchmark circuits show that this method can remove many sequential redundancies and reduce the number of gates and flip-flops.
Journal
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- Technical report of IEICE. VLD
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Technical report of IEICE. VLD 95 (307), 39-46, 1995-10-20
The Institute of Electronics, Information and Communication Engineers
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Details 詳細情報について
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- CRID
- 1571135652339901440
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- NII Article ID
- 110003294737
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- NII Book ID
- AN10013323
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- Text Lang
- ja
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- Data Source
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- CiNii Articles