マスクROMの故障解析とそのシグネチャ回路設計への応用

  • Iwasaki Kazuhiko
    Department of Information and Coputer Sciences,Faculty of Engineering,Chiba University
  • Furuta Akinori
    Department of Information and Coputer Sciences,Faculty of Engineering,Chiba University
  • Nakamura Shigeo
    Department of Information and Coputer Sciences,Faculty of Engineering,Chiba University

Bibliographic Information

Other Title
  • Fault Analysis in Mask ROM and its Application to Signature Circuit Design

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Description

マスクROMのワード, ビット線故障に対するエイリアス誤りを理論的に解析した.(x-α)(x-α^2)に基づくMISRでは、エイリアス確率が初期状態に依存することを証明した.故障を持つ1000個のマスクROMチップに対して,その故障原因を調べた.セル故障,ワード線故障,ビット線故障,遅延故障等が観測された.これらの故障チップに対し,BISTにおけるエイリアス誤りの実験をおこなった.6種類のMISRを基板上に実現した.その結果,エイリアス誤りが実際に生じることが観測された.16段8入力MISRではエイリアス確率が観測されず,6種類のMISRのうちでは最も良い性能を持つ.
The aliasing probability is theoretically analyzed for a mask ROM containing a word, bit-line fault or faults within a mat it is Proved that for the MISR characterized by(x-α)(x-α^2)the aliasing probability depends on its initial state.Faults were analyzed for 1,000 faulty mask ROM chips.Ceil faults,werd-line faults,bit-line faults,delay faults and others were observed.For these chips the BIST aliasing errors were experimentally examined.Six MISRs are implemented on a customu board.Aliasing errors were actually obsevved.The 16-stage MISR with 8-input had no aliasing error.This MISR is the best among six.

Journal

  • Technical report of IEICE. FTS

    Technical report of IEICE. FTS 93 (459), 15-22, 1994-02-10

    The Institute of Electronics, Information and Communication Engineers

Keywords

Details 詳細情報について

  • CRID
    1571135652355893632
  • NII Article ID
    110003206900
  • NII Book ID
    AN10012998
  • Text Lang
    en
  • Data Source
    • CiNii Articles

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