An Educational Course on Fully Interlocked Pipeline CISC/RISC Design : 2nd report of Microcomputer Design Educational Environment City-1

TAKAHASHI Ryuichi, YOSHIDA Noriyoshi

Bibliographic Information

Other Title

完全なインターロックを行なうパイプラインCISC/RISCの設計教育

Description

In City-1, the specification is given only by showing some application programs that should run on their machines. Every junior student designs not only his/her own instruction set but also his/her own hardware organization and his/her won bus architecture. Hardwired-controls and microprogrammed-controls are treated equally in a sense that the same code can be used for both of these controls. An incompletely described three sages pipelined CISC specification was given, as an example, with three-steps-operation using two-phase-clock-signals; a half clock cycle for the fetch, another half clock cycle for the decode and one clock cycle for the execution, emphasizing that the fully-interlocked-pipeline-design is the basics.

Journal

IPSJ SIG Notes

IPSJ SIG Notes 97 (103), 97-104, 1997

Information Processing Society of Japan (IPSJ)

Keywords

Details 詳細情報について

CRID: 1571417127175766528

NII Article ID: 110002930363

NII Book ID: AN1011091X

Text Lang: ja

Data Source

CiNii Articles

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