A 1.6G Byte/s Data-Rate 1Gb Synchronous DRAM with Hierarchical Square-Shaped Memory Block and Distributed Bank Architecture

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Bibliographic Information

Other Title
  • 階層型メモリブロックレイアウト方式と分散配置バンク構成を採用した200MHz 1GbitシンクロナスDRAMの設計技術

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Description

This paper describes key techniques for a 1.6G Byte/s high bandwidth 1Gb synchronous DRAM (SDRAM). Its high data transfer rate and large memory capacity are targeted to the advanced unified memory system in which a single DRAM (array) is used as both the main memory and the 3D graphics frame memory in a time sharing fashion. 200MHz high-speed operation is achieved by the unique hierarchical square-shaped memory block (SSMB) layout and the novel distributed bank (D-BANK) architecture. A 0.29μm^2 cell and 581.8mm^2 small die area are achieved using 0.15μm CMOS technology. The x64 chip uses 196-pin BGA type chip-scale-package (CSP). Implementation of a built-in self-test (BIST) circuit with a margin test capability is also described.

Journal

  • Technical report of IEICE. ICD

    Technical report of IEICE. ICD 96 (64), 53-58, 1996-05-23

    The Institute of Electronics, Information and Communication Engineers

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Keywords

Details 詳細情報について

  • CRID
    1571417127412868224
  • NII Article ID
    110003316521
  • NII Book ID
    AN10013276
  • Text Lang
    ja
  • Data Source
    • CiNii Articles

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