A 5-mW, 10-ns Cycle TLB Using a High-Performance CAM with Low-Power Match-Detection Circuits

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Description

Low-power, high-speed match-detection circuits for a content addressable memory (CAM) are proposed and evaluated. The circuits consist a current supply to a match-line, a differential amplifier, and 9-MOSFET CAM cells. The implementation of these circuits made it possible to realize a 16-entry, 32-bit data-compare CAM TEG of 1.2-ns match-detection time with 5-mW power dissipation in 10-ns cycle-time.

Journal

  • IEICE Trans. Electron.

    IEICE Trans. Electron. 79 (6), 757-762, 1996-06-25

    The Institute of Electronics, Information and Communication Engineers

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Details 詳細情報について

  • CRID
    1571417127440972800
  • NII Article ID
    110003211084
  • NII Book ID
    AA10826283
  • ISSN
    09168524
  • Text Lang
    en
  • Data Source
    • CiNii Articles

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