Dynamic Floating Body Control SOI CMOS for Power Managed Multimedia ULSIs

被引用文献1件 参考文献13件

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説明

A novel body potential-controlling technique for floating SOI CMOS circuits is proposed and verified in this study. High-speed operation is realized with a small chip size by using body-floating SOI transistors. The use of this technique allows the threshold voltage of the body-floating transistors to be varied transitionally. Therefore, the standby current of SOI CMOS logic is reduced to less than 1/50th of that required by the non-controlled operation of the body potential, and the logic operates at a high speed during the active period. There is no speed penalty for the recovery operation from the standby mode. This technique supports sub-1V operation, which will be required by future battery-operated devices with wide-range covering.

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詳細情報 詳細情報について

  • CRID
    1571417127442218496
  • NII論文ID
    110003212162
  • NII書誌ID
    AA10826283
  • ISSN
    09168524
  • 本文言語コード
    en
  • データソース種別
    • CiNii Articles

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