Design of Multi-Level NAND Flash Memories

TAKEUCHI Ken, TANAKA Tomoharu, NAKAMURA Hiroshi

Bibliographic Information

Other Title

NAND型フラッシュメモリの多値化の検討

Description

In a conventional NAND Flash Memory, the threshold voltages of the memory celled fluctuate due to array noise, named source line noise, during bit-by-bit program verify operation, and as a result the threshold voltage distribution becomes wider. The threshold voltage fluctuation is 0.7V in a conventional array. A new array architecture, "A Double-Level-V_<th> Select Gate Array Architecture" is proposed to eliminate the array noise, together with a reduction of the cell area. The threshold voltage fluctuation is as low as 0.03V in the proposed array and a high reliable operation of a Multi-Level NAND Flash Memory can be realized.

Journal

Technical report of IEICE. SDM

Technical report of IEICE. SDM 95 (380), 53-60, 1995-11-22

The Institute of Electronics, Information and Communication Engineers

Keywords

Details 詳細情報について

CRID: 1571698602396218624

NII Article ID: 110003309696

NII Book ID: AN10013254

Text Lang: ja

Data Source

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