An Analytic Steady-State Current-Voltage Characteristics of Short Channel Fully-Depleted Surrounding Gate Transistor (FD-SGT)
-
- ENDOH Tetsuo
- Research Institute of Electrical Communication, Tohoku University
-
- NAKAMURA Tairiku
- Research Institute of Electrical Communication, Tohoku University
-
- MASUOKA Fujio
- Research Institute of Electrical Communication, Tohoku University
Search this article
Description
A steady-state current-voltage characteristics of fully-depleted surrounding gate transistor (FD-SGT) with short channel effects, such as threshold voltage lowering and channel length modulation, is analyzed. First, new threshold voltage model of FD-SGT, which takes threshold voltage lowering caused by decreasing channel length into consideration, are proposed. We express surface potential as capacitance couple between channel and other electrodes such as gate, source and drain. And we analyze how surface potential distribution deviates from long channel surface potential distribution with source and drain effects when channel length becomes short. Next, by using newly proposed model, current-voltage characteristics equation with short channel effects is analytically formulated for the first time. In comparison with a three-dimensional (3D) device simulator, the results of newly proposed threshold voltage model show good agreement within 0.011 V average error. And newly formulated current-voltage characteristics equation also shows good agreement within 0.957% average error. The results of this work make it possible to clear the device designs of FD-SGT theoretically and show the new viewpoints for future ULSI's with SGT.
Journal
-
- IEICE Trans. Electronics
-
IEICE Trans. Electronics 80 (7), 911-917, 1997-07-25
The Institute of Electronics, Information and Communication Engineers
- Tweet
Details 詳細情報について
-
- CRID
- 1571698602418095616
-
- NII Article ID
- 110003211289
-
- NII Book ID
- AA10826283
-
- ISSN
- 09168524
-
- Text Lang
- en
-
- Data Source
-
- CiNii Articles
