Evaluating DRAM Refresh Architectures for Merged DRAM/Logic LSIs

9 References
  • OHSAWA Taku
    Department of Computer Science and Communication Engineering, Kyushu University
  • KAI Koji
    Institute of Systems & Information Technologies / KYUSHU
  • MURAKAMI Kazuaki
    Department of Computer Science and Communication Engineering, Kyushu University

Bibliographic Information

Other Title
  • DRAM/ロジック混載LSI向けDRAMリフレッシュ・アーキテクチャの評価

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Description

In merged DRAM/Iogic LSIs, it is nceessry to reduce the number of DRAM refrcshes because of higher heat dissipation caused by the logic portion on the same chip.In order to overcome this problem, we propose several DRAM refresh architectures.The basic idea behind them is to eliminate unnecessary DRAM refreshes.In addition we propose a method for reducing the number of DRAM refreshes by relocating data.In order to evaluate these architectures and method, we have estimated the DRAM refresh count in executing benchmark programs under several models which simulate each combination of them. As a result, in the most effective combination, we have obtained more than 80% reduction against a conventional DRAM refresh architecture for most of benchmark programs.In addition to it, we have taken normal DRAM access into account, even than we have obtained more then 50% reduction for several benchmarks.

Journal

  • Technical report of IEICE. VLD

    Technical report of IEICE. VLD 97 (576), 53-60, 1998-03-05

    The Institute of Electronics, Information and Communication Engineers

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Details 詳細情報について

  • CRID
    1571980077269329280
  • NII Article ID
    110003294551
  • NII Book ID
    AN10013323
  • Text Lang
    ja
  • Data Source
    • CiNii Articles

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