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A Delay-Locked Loop and 90-degree Phase Shifter for 800Mbps Double Data Rate Memories
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- YOSHIMURA Tsutomu
- System LSI Development Center, Mitsubishi Electric Corporation
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- NAKASE Yasunobu
- System LSI Development Center, Mitsubishi Electric Corporation
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- WATANABE Naoya
- ULSI Development Center, Mitsubishi Electric Corporation
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- MOROOKA Yoshikazu
- ULSI Development Center, Mitsubishi Electric Corporation
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- HYOZO Masahiko
- System LSI Development Center, Mitsubishi Electric Corporation
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- MATSUDA Yoshio
- System LSI Development Center, Mitsubishi Electric Corporation
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- KUMANOYA Masaki
- ULSI Development Center, Mitsubishi Electric Corporation
Bibliographic Information
- Other Title
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- 800Mbps動作DDRメモリ対応DLLおよび90°位相シフタ
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Description
This paper proposes an analog DLL for high-speed DDR memories. To minimize jitters, the DLL starts the lock-in process at the minimum delay of the delay line. But this DLL may lose the lock when the temperature increases. A finite-state machine is designed to solve the problem. We also proposes a 90-degree phase shifter with a small offset. The measured static phase offset is less than 120ps at the 2.5V and 800Mbps. This device is fabricated with 0.35μm CMOS technology.
Journal
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- IEICE technical report. Electron devices
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IEICE technical report. Electron devices 98 (117), 17-24, 1998-06-19
The Institute of Electronics, Information and Communication Engineers
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Details 詳細情報について
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- CRID
- 1571980077286703616
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- NII Article ID
- 110003200559
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- NII Book ID
- AN10012954
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- Text Lang
- ja
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- Data Source
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- CiNii Articles