フラッシュメモリセルアレイ用の新しい評価回路

7 References
  • HAZAMA H.
    Microelectronics Engineering Laboratory, Toshiba Corporation
  • HIMENO T.
    Microelectronics Engineering Laboratory, Toshiba Corporation
  • MATSUKAWA N.
    Semiconductor Quality Assurance Department, Toshiba Corporation
  • SAKUI K.
    Microelectronics Engineering Laboratory, Toshiba Corporation
  • OSHIKIRI M.
    Memory Division, Toshiba Corporation
  • MASUDA K.
    Microelectronics Engineering Laboratory, Toshiba Corporation
  • KANDA K.
    Microelectronics Engineering Laboratory, Toshiba Corporation
  • ITOH Y.
    Microelectronics Engineering Laboratory, Toshiba Corporation
  • MIYAMOTO J.
    Microelectronics Engineering Laboratory, Toshiba Corporation
  • HASHIMOTO K.
    Microelectronics Engineering Laboratory, Toshiba Corporation

Bibliographic Information

Other Title
  • A New Testing Methodology for Flash EEPROM Devices

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Description

フラッシュメモリセルアレイのしきい値電圧分布ならびにしきい値の最大値および最小値を有するセルのアドレスを検出する新しい評価回路を開発した。この回路を用いることにより、大規模セルアレイのしきい値分布を高速に測定でき、そのアレイ中でしきい値の最大値のアドレスおよび最小値のアドレスを高速に検出することが可能となった。この手法はフラッシュメモリセルの信頼性評価をセルアレイを有するテスト回路で可能にする。
A simple technique for measuring the threshold voltage distribution and detecting addresses of the cells with the maximum and the minimum threshold voltage in Flash EEPROM cell array is described. This circuit makes it possible to evaluate a large number of cell arrays within a reasonable time, and the address detection time for the cells with the maximum and the minimum threshold voltage is drastically reduced. The method enables reliability testing of Flash EEPROM using the test circuits.

Journal

  • Technical report of IEICE. SDM

    Technical report of IEICE. SDM 96 (151), 17-25, 1996-07-18

    The Institute of Electronics, Information and Communication Engineers

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Details 詳細情報について

  • CRID
    1571980077372923008
  • NII Article ID
    110003309633
  • NII Book ID
    AN10013254
  • Text Lang
    en
  • Data Source
    • CiNii Articles

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