An Analysis of A Data Cache : Dynamically Thread-Associative for Multithread Architecture

1 Citations 7 References
  • YAMAZAKI Shinya
    The Graduate School of Information Systems, The University of Electro-Communications
  • HONDA Hiroki
    The Graduate School of Information Systems, The University of Electro-Communications
  • YUBA Toshitsugu
    The Graduate School of Information Systems, The University of Electro-Communications

Bibliographic Information

Other Title
  • マルチスレッドアーキテクチャ用データキャッシュ-動的スレッドアソシアティブ方式-の評価

Search this article

Description

We have presented a new replacement algorithm in set-associative cache adapted to multithread architecture. By restricting the replacement candidate blocks to the sub-set in a set that exclusively assigned to each thread, the cache miss rate caused by the interference among threads can be kept low. This paper shows the result of the measurements on the cache simulator.

Journal

  • IPSJ SIG Notes

    IPSJ SIG Notes 132 97-102, 1999-03-04

    Information Processing Society of Japan (IPSJ)

Citations (1)*help

See more

References(7)*help

See more

Details 詳細情報について

  • CRID
    1572261551970198144
  • NII Article ID
    110002774746
  • NII Book ID
    AN10096105
  • ISSN
    09196072
  • Text Lang
    ja
  • Data Source
    • CiNii Articles

Report a problem

Back to top