An Algorithm for Finding a Minimal Three-Level NAND Network

Bibliographic Information

Other Title
  • 三段NANDゲート回路の一設計法

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Description

A method for the logical design of minimal three-level NAND gate network is proposed. First the P-N term method which is based on the idea cutting out N(egative permissible) terms from a P(ositive permissible) term is explained. Then the MA3 method being improved to apply to more variable functions is described. In the method, a multi-level NAND network is transformed to a three-level NAND network, P-terms are expanded to reduce the number of the second level gate, and a minimum cover table is used to reduce the number of input gates. The MA3 method is able to find the network for the whole of the function up to 9 variables and 10 variable functions which the truth-table-density are less than 0.55.

Journal

  • IPSJ SIG Notes

    IPSJ SIG Notes 93 (55), 47-54, 1993-06-25

    Information Processing Society of Japan (IPSJ)

Details 詳細情報について

  • CRID
    1572261552105897856
  • NII Article ID
    110002930379
  • NII Book ID
    AN1011091X
  • Text Lang
    ja
  • Data Source
    • CiNii Articles

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