High Yield Sub-0.1μm^2 6T-SRAM Cells, featuring High-k/Metal-Gate Finfet devices, Double Gate Patterning, a Novel Fin Etch Strategy, Full-Field EUV Lithography and Optimized Junction design & Layout

収録刊行物

• Digest of Technical Papers of 2010 Symposium on VLSI Technology

  Digest of Technical Papers of 2010 Symposium on VLSI Technology 22-23, 2010