An ASIC Design Methodology Using an Integrated Design Tool for FPGAs

  • Kobayashi K.
    Graduate School of Informatics, Kyoto University
  • Kanbara H.
    Graduate School of Informatics, Kyoto University Advanced Software Technology & Mechatronics Research Institute of KYOTO
  • Onodera H.
    Graduate School of Informatics, Kyoto University
  • Tamaru K.
    Graduate School of Informatics, Kyoto University

Bibliographic Information

Other Title
  • FPGA設計用統合環境を用いたASIC設計事例

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Description

Here, we compare ASIC design methodologies between MAX+PLUSII for FPGAs and conventional ASIC design environment by Verilog-HDL or VHDL. MAX+PLUSII is an FPGA design framework that integrates a schematic entry, an HDL Compiler and a simulator. If MAX can be applied to ASIC designs, designers can easily master the design flow owing to its user-friendly GUI environment. We apply the proposed MAX+PLUSII-based ASIC design methodology to two designs, "a BCD calculator", and "A Microprocessor for Education of Computer Hardware and LSI Design: Kuechip2". The proposed method achieves good performance and small area.

Journal

  • IPSJ SIG Notes

    IPSJ SIG Notes 98 (113), 147-152, 1998-12-10

    Information Processing Society of Japan (IPSJ)

Keywords

Details 詳細情報について

  • CRID
    1572543027083152512
  • NII Article ID
    110002930459
  • NII Book ID
    AN1011091X
  • Text Lang
    ja
  • Data Source
    • CiNii Articles

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