Power-Aware Scalable Pipelined Booth Multiplier
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- LEE Hanho
- School of Information and Communication Engineering, Inha University
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説明
An energy-efficient power-aware design is highly desirable for DSP functions that encounter a wide diversity of operating scenarios in battery-powered wireless sensor network systems. Addressing this issue, this letter presents a low-power power-aware scalable pipelined Booth multiplier that makes use of dynamic-range detection unit, sharing common functional units, ensemble of optimized Wallace-trees and a 4-bit array-based adder-tree for DSP applications.
収録刊行物
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- IEICE transactions on fundamentals of electronics, communications and computer sciences
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IEICE transactions on fundamentals of electronics, communications and computer sciences 88 (11), 3230-3234, 2005-11-01
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詳細情報 詳細情報について
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- CRID
- 1572543027319593216
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- NII論文ID
- 110003500485
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- NII書誌ID
- AA10826239
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- ISSN
- 09168508
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- 本文言語コード
- en
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- データソース種別
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