Single Chip Implementation of MPEG2 Decoder for HDTV Level Pictures

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Abstract

A single chip MPEG2 MP@HL video decoder has been developed, which consists mainly of specific functional units and macroblock level pipeline buffers. A new organization is also devised for a set of off-chip frame memories and the interfaces associated with it. Owing to sophisticated I/O interfaces among functional units, the macroblock level pipeline in conjunction with different decoding facilities attains a high throughput to such an extent as to decode HDTV images in real time. Moreover, a set of these functional units, pipeline buffers, and frame memory interfaces, together with a sequence controller, is integrated for the first time in a single chip, which has the total area of 8.8×9.2 mm^2 with a 0.6 μm triple-metal CMOS technology, and dissipates 1.2 W from a single 3.3 V supply.

Journal

  • IEICE Trans. Fundamentals

    IEICE Trans. Fundamentals 79 (3), 330-338, 1996-03-25

    The Institute of Electronics, Information and Communication Engineers

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Keywords

Details 詳細情報について

  • CRID
    1572543027348277248
  • NII Article ID
    110003216157
  • NII Book ID
    AA10826239
  • ISSN
    09168508
  • Text Lang
    en
  • Data Source
    • CiNii Articles

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