A High-Performance Set-Associative Cache Architecture with Speculative Way-Selection
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- INOUE Koji
- Department of Computer Science and Communication Engineering, Kyushu University
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- ISHIHARA Tohru
- Department of Computer Science and Communication Engineering, Kyushu University
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- MURAKAMI Kazuaki
- Department of Computer Science and Communication Engineering, Kyushu University
Bibliographic Information
- Other Title
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- 投機的ウェイ選択による高性能セット・アソシアティブ・キャッシュ方式とその性能評価
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Description
We have proposed a novel cache architecture for performance/energy efficiency, called"way-predictable set-associative cache(or way-predictable cache)". In general, conventional set-associative caches have several ways, and a only way is selected based on the result of tag comparisons. This process makes the cache access time longer. On the other hand, the way-predictable cache predicts a way having a data which will be referenced by the processor before tag comparisons. So, access speed of the way-predictable cache is faster than that of conventional set-associative caches due to the specurative way-selection. The way-predictable cache can achieve fast access just like direct-mapped caches, at the same time, higher hit rate is maintained due to set-associative method. We have quantitatively evaluated the way-predictable cache with many benchmarks. As the results, it is observed that the performance improvement achieved by an way-predictable cache is about 20%, compared to a conventional set-associative cache.
Journal
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- IEICE technical report. Computer systems
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IEICE technical report. Computer systems 98 (322), 35-42, 1998-10-15
The Institute of Electronics, Information and Communication Engineers
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Details 詳細情報について
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- CRID
- 1572824502243870336
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- NII Article ID
- 110003180283
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- NII Book ID
- AN10013141
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- Text Lang
- ja
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- Data Source
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- CiNii Articles