An implementation and performance evaluation of SNAIL:a multiprocessor based on the SSS-MIN
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- Sasahara Masashi
- Faculty of Science and Technology,Keio University
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- Terada Jun
- Faculty of Science and Technology,Keio University
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- Yamato Junichi
- Faculty of Science and Technology,Keio University
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- Amano Hideharu
- Faculty of Science and Technology,Keio University
Bibliographic Information
- Other Title
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- SSS型MINに基づくマルチプロセッサSNAILの実装と評価
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Description
Simple Serial Synchronized(SSS)Multistage Interconnection Network(MIN)is a novel MIN architecture for connecting processors and memory modules in multiprocessors.Synchronized bit-serial communication simplifies the structure, control,and also solves the pin-limitation problem.The simple structure allows the use of a high frequency clock rate and a high throughput network topology. An LSI implementation of the SSS-MIN has been completed. Using these chips,a multiprocessor prototype called SNAIL with 16 processors, 16 memory modules is under development,and a system with 4 processors/4 memory modules is operational.The small overhead of the SSS-MIN is demonstrated with some parallel benchmark programs.The performance enhancement mechanisms such as data prefetch and message combining are also evaluated.
Journal
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- IEICE technical report. Computer systems
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IEICE technical report. Computer systems 93 (181), 9-16, 1993-08-19
The Institute of Electronics, Information and Communication Engineers
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Keywords
Details 詳細情報について
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- CRID
- 1572824502245398016
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- NII Article ID
- 110003180014
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- NII Book ID
- AN10013141
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- Text Lang
- ja
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- Data Source
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- CiNii Articles