Circuit Technique for Skew-Free Clock Distribution

SUTOH Hiroki, HATANO Takahiro, YAMAKOSHI Kimihiro, INO Masayuki

Bibliographic Information

Other Title

クロック分配用スキュー補正回路の検討

Description

This Paper describes a clock distribution technique for multiple targets that employs an automatic skew compensation circuit. Using this technique keeps clock skew among multiple targets below the resolution time of the variable delay lines without any manual adjustment. Measured experimental results show that the initial clock skew of 900ps is cancelled automatically and 30ps clock skew is achieved at a clock frequency of up to 250MHz with 60ps clock jitter.

Journal

Technical report of IEICE. ICD

Technical report of IEICE. ICD 95 (218), 37-42, 1995-08-25

The Institute of Electronics, Information and Communication Engineers

Keywords

Details 詳細情報について

CRID: 1572824502297916928

NII Article ID: 110003316953

NII Book ID: AN10013276

Text Lang: ja

Data Source

CiNii Articles

Export

Report a problem