A Bi-Linear Interpolation Unit Using Selector Logics
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- SHIO Masashi
- Dept. of Computer Science and Engineering, Waseda University
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- YANAGISAWA Masao
- Dept. of Computer Science and Engineering, Waseda University
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- TOGAWA Nozomu
- Dept. of Computer Science and Engineering, Waseda University
Bibliographic Information
- Other Title
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- セレクタ論理を利用したバイリニア補間演算器設計と評価(システムLSIの応用とその要素技術,専用プロセッサ,プロセッサ,DSP,画像処理技術,及び一般)
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Description
Bi-Linear interpolation is one of interpolation techniques, which interpolates a value linearly from its four circumferences. Bi-Linear interpolation is often used for image scaling and correction of distortion. In this paper, we propose a high-speed bi-linear interpolation circuit reducing carry propagation delay by using selector logics. We have implemented our bi-linear interpolation circuit in several ways and evaluated each of them.
Journal
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- Technical report of IEICE. VLD
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Technical report of IEICE. VLD 113 (235), 53-58, 2013-09-30
The Institute of Electronics, Information and Communication Engineers
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Details 詳細情報について
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- CRID
- 1572824502717748992
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- NII Article ID
- 110009821695
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- NII Book ID
- AN10013323
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- Text Lang
- ja
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- Data Source
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- CiNii Articles