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A Novel Cell Structure with Bit Line Cap Spacer (BCS) and Top Enlarged Storage Node Contact (TESC) for 90nm DRAM Technology and Beyond
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- YUN C. J.
- DRAM Process Architecture Team, Samsung Electronics Co., Ltd.
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- PARK Y. K.
- DRAM Process Architecture Team, Samsung Electronics Co., Ltd.
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- LEE J. W.
- DRAM Process Architecture Team, Samsung Electronics Co., Ltd.
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- BAE D. I.
- DRAM Process Architecture Team, Samsung Electronics Co., Ltd.
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- KIM S. B.
- DRAM Process Architecture Team, Samsung Electronics Co., Ltd.
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- SHIN S. H.
- DRAM Process Architecture Team, Samsung Electronics Co., Ltd.
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- LEE J. G.
- DRAM Process Architecture Team, Samsung Electronics Co., Ltd.
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- LEE S. H.
- DRAM Process Architecture Team, Samsung Electronics Co., Ltd.
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- LEE D. J.
- DRAM Process Architecture Team, Samsung Electronics Co., Ltd.
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- LEE E. C.
- DRAM Process Architecture Team, Samsung Electronics Co., Ltd.
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- ROH B. H.
- DRAM Process Architecture Team, Samsung Electronics Co., Ltd.
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- NAM I. H.
- DRAM Process Architecture Team, Samsung Electronics Co., Ltd.
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- CHUNG T. Y.
- DRAM Process Architecture Team, Samsung Electronics Co., Ltd.
Search this article
Journal
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- Extended abstracts of the ... Conference on Solid State Devices and Materials
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Extended abstracts of the ... Conference on Solid State Devices and Materials 2004 756-757, 2004-09-15
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Details 詳細情報について
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- CRID
- 1573105975462112768
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- NII Article ID
- 10022540010
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- NII Book ID
- AA10777858
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- Text Lang
- en
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- Data Source
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- CiNii Articles
