A loop restructuring technique to optimize memory access locality

  • TSUDA TAKESHI
    Division of Communications and Computer Engineering, Graduate School of Infomatics, Kyoto University
  • YAMAMOTO TAKANOBU
    Division of Communications and Computer Engineering, Graduate School of Infomatics, Kyoto University
  • TANAKA TOSHIHIKO
    Division of Communications and Computer Engineering, Graduate School of Infomatics, Kyoto University
  • GOSHIMA MASAHIRO
    Division of Communications and Computer Engineering, Graduate School of Infomatics, Kyoto University
  • MORI SHIN-ICHIRO
    Division of Communications and Computer Engineering, Graduate School of Infomatics, Kyoto University
  • TOMITA SHINJI
    Division of Communications and Computer Engineering, Graduate School of Infomatics, Kyoto University

Bibliographic Information

Other Title
  • メモリ・アクセスの局所性を最適化するループ再構成法

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Description

It is known that a loop optimize technique, Tiling can be applied to each class of memory hierarchy, In this paper, we speak about the technique to apply tiling for the size of each class of memory hierarchy and decide the size of the tile and the order of loop so that hit ratio of each memory hierarchy is improved, The best size of a certain level of memory hierarchy is contray to that of former level. In this technique, we know that tile size can be decided by only slow memory hierarchy. We decide the order of loop to make use of the size of memory hierarchy. When we apply this technique to matrix product and lu decomposition, the performance is not decreased when the size is larger. In lu decomposition, we get 26% better result than the former technique.

Journal

  • IPSJ SIG Notes

    IPSJ SIG Notes 99 (21), 133-138, 1999-03-04

    Information Processing Society of Japan (IPSJ)

Details 詳細情報について

  • CRID
    1573105976798792960
  • NII Article ID
    110004752365
  • NII Book ID
    AN10463942
  • Text Lang
    ja
  • Data Source
    • CiNii Articles

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